The present invention relates to an image signal processor, and, more particularly, to an image signal processor and a deficient pixel detection method which detect a deficiency contained in image signals and correct the deficiency.
Solid state image pickup devices, such as CCD image sensors, may store a constant charge in a pixel regardless of the level of the received light. As a result, the pixel becomes a deficient pixel and outputs an image signal of a fixed level.
To eliminate the influence of deficient pixels on an image reproduction screen, deficiency correction is performed on the image signals of deficient pixels acquired from the solid state image pickup device.
FIG. 1 is a schematic block diagram of an image pickup device 100. The pickup device 100 has a CCD image sensor 1, a drive circuit 2, a timing control circuit 3, a signal processing circuit 4, a deficiency correction circuit 5 and a correction information memory 6.
The CCD image sensor 1 has a matrix of light receiving pixels (not shown) which store charges according to the received image of a subject. The CCD sensor 1 transfers charges stored in the individual light receiving pixels line by line in accordance with a vertical drive signal φV and a horizontal drive signal φH, and produces an image signal Y0 according to a predetermined format.
The drive circuit 2 produces the vertical drive signal φV and horizontal drive signal φH for driving the CCD image sensor 1 in accordance with a vertical sync signal VD and a horizontal sync signal HD, and sends those drive signals to the CCD image sensor 1.
The timing control circuit 3 frequency-divides a reference clock having a given period to thereby produce the vertical sync signal VD that determines the vertical scan timing and the horizontal sync signal HD that determines the horizontal scan timing, and sends the sync signals VD and HD to the drive circuit 2. In the NTSC format, for example, the horizontal sync signal HD is produced by frequency-dividing a reference clock of 14.32 MHz by 910, and the vertical sync signal VD is produced by frequency-dividing the horizontal sync signal by 525/2. The timing control circuit 3 supplies the signal processing circuit 4 and the deficiency correction circuit 5 with a timing signal synchronous with the operational timing of the CCD image sensor 1.
The signal processing circuit 4 performs a sample and hold process and level correction on the image signal Y0 supplied from the CCD image sensor 1, thereby generating an image signal Y1. The image signal Y0 repeats a signal level and reset level. In the sample and hold process, the signal processing circuit 4 produces the image signal Y1 having the signal level from the image signal Y0 by clamping the reset level, for example. In the level correction, the signal processing circuit 4 performs gain feedback control on the image signal Y0 in such a manner that the average level of the image signal Y1 lies in a target range. The signal processing circuit 4 samples and holds the image signal Y0 and performs A/D conversion on the resultant image signal Y0, thus yielding a digital image signal Y1.
The deficiency correction circuit 5 adjusts the image signal Y1 using correction information stored in the correction information member 6. For instance, information of a deficient pixel is replaced with the average value of information of pixels before and after the deficient pixel.
The correction information member 6 stores the positions of deficient pixels of the CCD image sensor 1. For example, the positions of deficient pixels are detected by monitoring the output of the CCD image sensor 1 beforehand, and the detection result is stored as correction address information in the memory 6.
Even when plural CCD image sensors 1 are constructed from semiconductor substrates that have been manufactured with the same process, the positions of deficient pixels differ from one sensor to another. It is therefore necessary to generate correction address information by detecting the positions of deficient pixels for each CCD image sensor 1. This increases the cost involved in the assembling process.
The number of deficient pixels in the CCD image sensor 1 may increase with time. When such time-dependent changes occur, the correction address information in the correction information member 6 should be rewritten. However, ordinary users of image pickup devices do not have means for rewriting the contents of the correction information memory 6. This makes it harder to rewrite the correction address information.